1. Field of the Invention
The present invention relates in general to the control of a motion compensation circuit for video processing systems employing a digital video compression manner such as a high definition television (referred to hereinafter as "HDTV"), a video phone, a moving picture expert group (referred to hereinafter as MPEG), a karaoke, a multimedia, etc., and more particularly to a memory address and display control apparatus for an HDTV in which an address is generated from a memory address controller for motion compensation of the HDTV and then efficiently interfaced with a frame memory unit; data input/output of the frame memory unit are controlled by an input/output controller; a display read control circuit is provided in the memory address controller to read video data stored in the unit of block in the frame memory unit in a raster scanning manner and to display the read video data on a screen; and luminance and color difference signals are separated from the video data from the frame memory unit by a display controller.